Semiconductor device with doped transistor

ABSTRACT

A semiconductor device provides a substrate having a first region and a second region. A sacrificial first gate is formed in the first region. Source/drain are formed in the first region. A second region gate dielectric is formed in the second region. A second region gate is formed on the second region gate dielectric. A second region source/drain is formed in the second region. A sacrificial layer is formed over the sacrificial first gate, the source/drain, the first region, and the second region. The sacrificial first gate is exposed. A gate space is formed by removing the sacrificial first gate. A first region gate dielectric is formed in the gate space. A first region gate is formed on the first region gate dielectric. The sacrificial layer is removed.

CROSS-REFERENCE TO RELATED APPLICATION(S)

This is a divisional of co-pending application Ser. No. 10/908,328 filedMay 6, 2005, which is hereby incorporated by reference thereto.

TECHNICAL FIELD

The present invention relates generally to semiconductor transistors,and more particularly to a doped transistor.

BACKGROUND ART

At the present time, electronic products are used in almost every aspectof life, and the heart of these electronic products is the integratedcircuit. Integrated circuits are used in everything from airplanes andtelevisions to wristwatches.

Integrated circuits are made in and on silicon wafers by extremelycomplex systems that require the coordination of hundreds or eventhousands of precisely controlled processes to produce a finishedsemiconductor wafer. Each finished semiconductor wafer has hundreds totens of thousands of integrated circuits, each wafer worth hundreds orthousands of dollars.

Integrated circuits are made up of hundreds to millions of individualcomponents. One common component is the semiconductor transistor. Themost common and important semiconductor technology presently used issilicon-based, and the most preferred silicon-based semiconductor deviceis a complementary metal oxide semiconductor (“CMOS”) transistor.

The principal elements of a CMOS transistor generally consist of asilicon substrate having shallow trench oxide isolation regionscordoning off transistor areas. The transistor areas contain polysilicongates on silicon oxide gates, or gate dielectrics, over the siliconsubstrate. The silicon substrate on both sides of the polysilicon gateis slightly doped to become conductive. These lightly doped regions ofthe silicon substrate are referred to as “shallow source/drain”, whichare separated by a channel region beneath the polysilicon gate. A curvedsilicon oxide or silicon nitride spacer, referred to as a “sidewallspacer”, on the sides of the polysilicon gate allows deposition ofadditional doping to form more heavily doped regions of the shallowsource/drain (“S/D”), which are called “deep S/D”.

To complete the transistor, a silicon oxide dielectric layer isdeposited to cover the polysilicon gate, the curved spacer, and thesilicon substrate. To provide electrical connections for the transistor,openings are etched in the silicon oxide dielectric layer to thepolysilicon gate and the S/D. The openings are filled with metal to formelectrical contacts. To complete the integrated circuits, the contactsare connected to additional levels of wiring in additional levels ofdielectric material to the outside of the dielectric material.

As electronic circuits become increasingly complex, the need increasesto combine high voltage transistors with low voltage transistors on anintegrated circuit. High voltage transistors are found in devices suchas liquid crystal display drivers and power management circuits. Lowvoltage transistors are found in devices such as high density staticrandom access memory.

One type of high voltage transistor is a double diffused source/drain(“DDD”). High voltage DDD transistors are formed with processes usinghigh energy implants and high thermal cycles. Unfortunately, theseprocesses are harmful to low voltage transistors.

Solutions to these problems have been long sought but prior developmentshave not taught or suggested any solutions and, thus, solutions to theseproblems have long eluded those skilled in the art.

DISCLOSURE OF THE INVENTION

The present invention provides a semiconductor device. A substrate isprovided having a first region and a second region. A sacrificial firstgate is formed in the first region. Source/drain are formed in the firstregion. A second region gate dielectric is formed in the second region.A second region gate is formed on the second region gate dielectric. Asecond region source/drain is formed in the second region. A sacrificiallayer is formed over the sacrificial first gate, the double diffusedsource/drain, the first region, and the second region. The sacrificialfirst gate is exposed. A gate space is formed by removing thesacrificial first gate. A first region gate dielectric is formed in thegate space. A first region gate is formed on the first region gatedielectric. The sacrificial layer is removed.

Certain embodiments of the invention have other advantages in additionto or in place of those mentioned above. The advantages will becomeapparent to those skilled in the art from a reading of the followingdetailed description when taken with reference to the accompanyingdrawings.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 is a cross sectional view of an integrated high voltage/lowvoltage transistor device in an intermediate stage of manufacture inaccordance with an embodiment of the present invention;

FIG. 2 is the structure of FIG. 1 after further processing and theaddition of a double diffused source/drain;

FIG. 3 is the structure of FIG. 2 after further processing and additionof a low voltage gate, lightly doped source/drains, first dielectriclayer, second dielectric layer, and sacrificial dielectric layer;

FIG. 4 is the structure of FIG. 3 after further processing and chemicalmechanical planarization of the sacrificial dielectric layer;

FIG. 5 is the structure of FIG. 4 after further processing and additionof a high voltage gate dielectric and a high voltage gate;

FIG. 6 is the structure of FIG. 5 after further processing and removalof the sacrificial dielectric layer and the second dielectric layer;

FIG. 7 is the structure of FIG. 6 after further processing and additionof low voltage source/drain and high voltage source/drain; and

FIG. 8 is a flow chart of a method for manufacturing a semiconductordevice in accordance with an embodiment of the present invention.

BEST MODE FOR CARRYING OUT THE INVENTION

In the following description, numerous specific details are given toprovide a thorough understanding of the invention. However, it will beapparent that the invention may be practiced without these specificdetails. In order to avoid obscuring the present invention, somewell-known circuits and process steps are not disclosed in detail.

Likewise, the drawings showing embodiments of the device aresemi-diagrammatic and not to scale and, particularly, some of thedimensions are for the clarity of presentation and are shown exaggeratedin the FIGs. The same numbers are used in all the drawing FIGs. torelate to the same elements.

The term “horizontal” as used herein is defined as a plane parallel tothe conventional plane or surface of the substrate or wafer, regardlessof its orientation. The term “vertical” refers to a directionperpendicular to the horizontal as just defined. Terms, such as “on”,“above”, “below”, “bottom”, “top”, “side” (as in “sidewall”), “higher”,“lower”, “over”, and “under”, are defined with respect to the horizontalplane.

The term “processing” as used herein includes deposition of material orphotoresist, patterning, exposure, development, etching, cleaning,and/or removal of the material or photoresist as required in forming adescribed structure.

As the demand for chip performance and functionality increases, there isan increasing need for the integration of low voltage (“LV”)complementary metal oxide semiconductor (“CMOS”), less than about 5V,with high voltage (“HV”) CMOS, about 20V-600V, on the same chip.However, HV CMOS technology preferably uses double diffused source/drain(“DDD”) transistors. DDD transistors are formed with high energyimplants, about 100 KeV to 1000 KeV, and high thermal drive-in cycles,greater than 800° C. However, high energy implants and high thermaldrive-in cycles are not compatible with LV CMOS technology. Thus,problems occur when applying conventional techniques to integrate highvoltage DDD transistors with deep submicron high density low leakagetechnology such as static random access memory (“SRAM”) devices.

One problem occurs with formation of a thick gate dielectric, forexample greater than 400 Å, for HV CMOS devices. Removal of the thickgate dielectric from the LV CMOS devices causes divots to form inshallow trench isolations (“STI”) of the LV CMOS devices. The divots areformed from trapped acid, such as HF acid, which etches more of the STI.The divots make the LV CMOS devices leak current and have low yield as aresult.

Another problem occurs during high energy DDD implants done after gateelectrode patterning. Polysilicon gate electrodes, being common for LVCMOS and HV CMOS, are relatively thin (1500 Å to 2500 Å) and thereforecannot block DDD implant species at 100 to 1000 KeV energy range in theHV channel area.

Yet another problem occurs during drive-in processes. HV CMOS devicesrequire higher thermal budgets (900-1050° C. for 30 to 60 minutes) forjunction drive-in. However, LV CMOS devices cannot tolerate longerthermal budgets after gate patterning.

Referring now to FIG. 1, therein is shown a cross sectional view of anintegrated HV/LV transistor device 100 in an intermediate stage ofmanufacture in accordance with an embodiment of the present invention. Asubstrate 102, of a material such as silicon (“Si”), has STIs 104,filled with a dielectric of a material such as silicon dioxide (“SiO₂”).

Between the STIs 104 are a low voltage LV CMOS device region 106 and aHV CMOS device region 108 in an intermediate stage of manufacture. TheLV CMOS device region 106 is used for devices such as high density SRAM.The HV CMOS device region 108 is used for devices such as liquid crystaldisplay (“LCD”) drivers and power management circuits.

On top of the substrate 102 and the STIs 104 is a sacrificial dielectriclayer 110 of a material such as SiO₂, about 100-200 Å thick. Asacrificial HV gate 112, of another dielectric material, such as siliconnitride, is formed on the sacrificial dielectric layer 110 of the HVCMOS device region 108. The sacrificial HV gate 112 measures vertically0.2 μm to 1.2 μm.

Referring now to FIG. 2, therein is shown the structure of FIG. 1 afterfurther processing. The sacrificial HV gate 112 and a mask 114 allow ahigh energy implant 202 of the HV CMOS device region 108. The highenergy implant 202, followed by a thermal drive-in, forms DDDs 204. TheDDDs 204 are self-aligned to the sacrificial HV gate 112.

Due to the higher blocking power of the thick nitride of the sacrificialgate 112 preventing penetration in HV channel region, the energy of theDDD implants in this case can be high, about 100-1000 KeV, and hence therequirement of long diffusion thermal cycles to achieve deeper DDDjunctions is minimized. Several problems with the prior art are solvedby the completion of the LV CMOS device region 106 with the high energyimplant 202 and the long thermal drive.

Because the gate of the LV CMOS device region 106 has not yet beenformed, the high energy implant 202 and long drive cannot damage thegate.

Also, because the LV structures and implants have not yet been formed onthe LV CMOS device region 106, the high thermal budget drive for formingthe DDD 204 of the HV CMOS device region 108 cannot effect the LVstructures and implants. This results in a graded profile of the DDD 204and high voltage capability.

Referring now to FIG. 3, therein is shown the structure of FIG. 2 afterfurther processing of removing the mask 114 (FIG. 2) and the sacrificialdielectric layer 110 (FIG. 2), growing a LV gate dielectric 306,depositing a gate electrode poly-silicon layer (not shown) which afterphotolithographic processing forms a LV gate 302 in the LV CMOS deviceregion 106. The LV gate 302 is thinner than the HV gate 506 (FIG. 5).Lightly doped source/drains (“LDDs”) 304 are formed in the LV CMOSdevice region 106 using standard implant procedures (not shown).

An etch removes the sacrificial dielectric layer 110 (FIG. 2) leaving asacrificial HV gate dielectric 308. A first liner 310 of a dielectriclayer, such as tetraethyl orthosilicate (“TEOS”), is formed over thesacrificial HV gate 112. A second liner 311 of a dielectric layer, suchas TEOS, is formed over the LV gate 302. A prespacer layer 312 ofanother dielectric material, such as SiN, is formed over the STIs 104,the LDDs 304, the first liner 310, the second liner 311, and the DDDs204. A sacrificial layer 314 of a dielectric layer, such as TEOS, isformed over the prespacer layer 312.

Referring now to FIG. 4, therein is shown the structure of FIG. 3 afterfurther processing. A chemical mechanical planarization (“CMP”) (notshown), such as an oxide CMP, is performed on the sacrificial layer 314.The CMP exposes a top surface 402 of the sacrificial HV gate 112.

Referring now to FIG. 5, therein is shown the structure of FIG. 4 afterfurther processing. The sacrificial HV gate 112 (FIG. 4), thesacrificial HV gate dielectric 308 (FIG. 4), and the first liner 310(FIG. 4) are removed by phosphoric acid and a hydrofluoric acid dip.Thus a gate space 502 is formed.

A chemical vapor deposited dielectric, such as SiO₂, lines the gatespace 502, forming a HV gate dielectric 504 of the HV CMOS device region108. In one embodiment, the HV gate dielectric 504 is formed, forexample to a thickness greater than 400 Å. During formation of the HVgate dielectric 504, the sacrificial layer 314 and the prespacer layer312 protect the STIs 104. Thus, divot formation in the STIs 104 isavoided, thereby solving the problem of leaky, low yield LV CMOS devicescaused by divots.

The gate space 502 is filled with in situ doped polysilicon or metal,such as aluminum, and forms a HV gate 506. A CMP is performed on thesacrificial layer 314 down to the HV gate dielectric 504.

Referring now to FIG. 6, therein is shown the structure of FIG. 5 afterfurther processing. An isotropic etch removes the sacrificial layer 314(FIG. 5) and the exposed regions of the HV gate dielectric 504 on eitherside of the HV gate 506. An anisotropic etch then etches the prespacerlayer 312 (FIG. 5), thus forming a LV spacer 602 around the LV gate 302.

Referring now to FIG. 7, therein is shown the structure of FIG. 6 afterfurther processing. Standard back end of line processes are used to formthe remaining structures, such as LV source/drains 702 and HVsource/drains 704, to complete the integrated HV/LV transistor device100.

Referring now to FIG. 8, therein is shown a flow chart of a method 800for manufacturing a semiconductor device in accordance with the presentinvention. The method 800 includes providing a substrate having a firstregion and a second region in a block 802; forming a sacrificial firstgate in the first region in a block 804; forming source/drain in thefirst region in a block 806; forming a second region gate dielectric inthe second region in a block 808; forming a second region gate on thesecond region gate dielectric in a block 810; forming a second regionsource/drain in the second region in a block 812; forming a sacrificiallayer over the sacrificial first gate, the double diffused source/drain,the first region, and the second region in a block 814; exposing thesacrificial first gate in a block 816; forming a gate space by removingthe sacrificial first gate in a block 818; forming a first region gatedielectric in the gate space in a block 820; forming a first region gateon the first region gate dielectric in a block 822; and removing thesacrificial layer in a block 824.

Thus, it has been discovered that the semiconductor device method andapparatus of the present invention furnish important and heretoforeunknown and unavailable solutions, capabilities, and functionaladvantages for integrating the manufacture of high voltage DDDtransistors with low voltage transistors on the same chip. The resultingprocesses and configurations are straightforward, economical,uncomplicated, highly versatile and effective, can be implemented byadapting known technologies, and are thus fully compatible withconventional manufacturing processes and technologies.

While the invention has been described in conjunction with a specificbest mode, it is to be understood that many alternatives, modifications,and variations will be apparent to those skilled in the art in light ofthe aforegoing description. Accordingly, it is intended to embrace allsuch alternatives, modifications, and variations which fall within thescope of the included claims. All matters hithertofore set forth hereinor shown in the accompanying drawings are to be interpreted in anillustrative and non-limiting sense.

1. A semiconductor device, comprising: a substrate; a first region inthe substrate; a double diffused source/drain in the first region; afirst region gate dielectric in the first region; a first region gate onthe first region gate dielectric; a second region in the substrate; asecond region gate in the second region, the second region gate beingthinner than the first region gate; and a second region source/drain inthe second region.
 2. The semiconductor device of claim 1 wherein thedouble diffused source/drain is self-aligned.
 3. The semiconductordevice of claim 1 further comprising a second region gate dielectric inthe second region.
 4. The semiconductor device of claim 1 furthercomprising a shallow source/drain in the second region.
 5. Thesemiconductor device of claim 1 wherein the first region gate uses dopedpolysilicon or metal.
 6. A semiconductor device, comprising: asubstrate; a high voltage device region in the substrate; a doublediffused source/drain in the high voltage device region; a high voltagegate dielectric in the high voltage device region having a thicknessgreater than 400 Å; a high voltage gate on the high voltage gatedielectric a high voltage source/drain; a low voltage device region inthe substrate; a low voltage gate in the low voltage device region; alow voltage spacer around the low voltage gate; a low voltagesource/drain in the low voltage device region; and shallow trenchisolations between and around the high voltage device region and the lowvoltage device region.
 7. The semiconductor device of claim 6 whereinthe double diffused source/drain is self-aligned.
 8. The semiconductordevice of claim 6 further comprising a low voltage gate dielectric inthe low voltage device region.
 9. The semiconductor device of claim 6further comprising a low voltage lightly doped source/drain in the lowvoltage device region.
 10. The semiconductor device of claim 6 whereinthe high voltage gate uses doped polysilicon or metal.